FPGAs

RAM (and sometimes EEPROM or AntiFuse) based ispGALs are called Field Programmable Gate Arrays (FPGAs).

Gates are logic gates, like And, Or, Not, and the lovely NAND (Not AND, an and gate with a not gate on the output). Array means there are a crap ton of those, and believe it or not, you can make just about anything given enough logic gates... Add, subtract, compare, multiply, sequence, count, etc... And Field Programmable means you can connect them together in any way you like.

RAM based devices must be reprogrammed each time on power up (which requires time and introduces a delay that may be unacceptable in some applications) but can be reprogrammed as often as desired. EEPROM is permenant but can only be reprogramed a few hundred times and AntiFuse is One Time Programmable. FPGAs typically do not have deterministic timing. i.e. the amount of time for a signal to get from point A to point B may not always be the same depending on which gates get assigned to which function in your design. Power consuption is typically lower than for CPLDs. FPGA typically conatin many Flip-Flops and IO gates. They are commonly used for:

• Logic consolidation
• Board integration
• Replace obsolete devices
• Simple state machines
• Complex controllers/interfaces

PIClist Thread: "Getting started with FPGA" (2007) mentions these sources of low-cost programmer/dev kits:

• eBay
• ask your local FAE or distributor -- sometimes they give away development kits, in order to gain or win design sockets
• Xilinx WebPack has a simulator
• Altera CycloneII FPGA Starter Board
• Digilent, Inc. has some nice FPGA prototyping boards, some for under $100 (using Xilinx chips)
• Sparkfun Spartan 3E Breakout and Development Board + Xilinx FPGA Parallel Programmer

CPLDs

FLASH (and sometimes EPROM or EEPROM) based ispGALs are called Complex Programmable Logic Devices (CPLDs). Hold thier programming in non-volitile memory and so fire up ready to go. Unfortunatly, these types of memory do have a limited life so CPLDs can not be reprogrammed continuosly. Many CPLDs do have deterministic timing since the signals are routed between macrocells via interconnects. Signals travel from pin to pin very quickly. Common applications inlcude:

• Bus interfaces
• Complex state machines
• Fast memory interfaces
• Wide decoders
• PAL-device integration

Software to translate HDL description of circuits into JDEC files, program the JDEC files into the individual devices and the interconnection cable between the PC and the device via an adapter socket or ISP header costs thousands of dollars. You can get started for quite a bit less.

Xilinx sells a student edition for about $99. It is crippled in that it is limited in the size device it can compile. Still, the devices it handles are plenty big to do many things, especially learn about the device capabilities.

That package has a schematic entry capture tool. While the industry is pushing hard toward text based entry, lack of knowledge of the device architecture will not let you exploit the device to anywhere near its potential. I highly recommend newbies start out with schematic entry and use it until they at least become comfortable with the device structure and tools and what works and doesn't work. Once you have that down, then you are welcome to fight with the VHDL tools to make them do what you've learned is the best implementation for what you want to do.

One of the weaknesses of the foundation schematic capture is its poor handling of hierarchy. In viewlogic, you can easily encapsulate a design as a macro to be used in a larger design. XILINX says it will improve this with version 2.1i expected in fall

See also:

• Circuit Celler Ink #65 December 1995 "In-Circuit-Programmable GALs" and "Low-Cost FPGA Programmer"
• Three FPGAs (Xilinx Virtex, Lucent Orca3, Atmel AT40K) and three CPLDs (Vantis Mach5, Lattice ispLSI 5000V and Philips XPLA2). Article and Addendum (with all the data):
• FPGA to CPLD comparison