SX MultiMediaCard (MMC) Interface

Introduction

This application note presents programming techniques for reading and writing via a simple three-pin SPI interface (and optional fourth pin card select output) to an external MMC card. The MMC is ideal for small form-factor applications because it is less than half the size of a regular half-size PCMCIA card such as compactflash and can contain up to 64Meg of data and is removable, stackable and PC configurable.

In this implementation, the data stored on the MMC is streamed into the SX using a circular buffer and sent out as a mono or stereo audio signal through a pair of pulse-width-modulated (PWM) outputs. The hardware also offers the option of reading an incoming audio signal using a sigma-delta analog-to-digital converter which uses the same PWM output RC network in reverse and converts the incoming analog (audio) signal to a bitstream input.

How the circuit and program work

The analog output circuit is a simple resistor capacitor network on each PWM port pin. This RC combination acts as a digital-to-analog (D/A) output by integrating the changing bitstream signal coming from the SX. The output is then AC-coupled to provide an AC audio signal output.

The interrupt code segment contains both the ADC input and PWM output code segments, as well as a circular buffer that is filled with data from the MMC streaming in through a main-line MMC block read subroutine via the SPI port pins. The main line code also contain an MMC command interpreter subroutine that performs all required functions for accessing the MMC, such as initialization, reading, writing, etc.

A circular buffer is required because the MMC can only be read in block read mode of 512 bytes per block when using the SPI protocol to access the card. Therefore, data from an entire block cannot be stored on the card. With an oscillator frequency of 50MHz, the SPI bit-read loop is optimized to 9 cycles, permitting a read transfer rate of slightly over 600k bytes/sec. Data is read in considerably faster than it is output to the PWMs, however there are significant delays between blocks while reading the CRC bytes and setting up the next block, etc. The buffer allows for a streamlined synchronous output through the PWM with the aid of a frequency timer virtual peripheral in the interrupt code loop. The timer triggers at a fixed interval which is the sample output rate. Upon each trigger, the next data byte is fed from the circular buffer to the PWM output.

As for using the RC networks as ADC inputs, this is described in a separate application note and should be referenced in conjunction with the frequency limitations. This method for D/A and A/D conversion is effective for signals whose highest frequency component is lower than half of the lowest frequency possible by the PWM virtual peripheral. The sample output period of the PWM cycle (in turbo mode) is calculated as follows:

period (sec) = prescaler * RETIW value / osc. frequency

So, for an 8-bit output signal, the PWM needs up to 256 interrupt passes to completely settle to the intended voltage. At a crystal frequency of 50 MHz, with a prescaler of 1, and with an RETIW value of 46, the highest frequency possible by the PWM output is:

frequencypwm = 1 / period * 256 *2 = 50 MHz / (1 * 46 * 256 ) = 4.25 kHz

By this we can also see that the ADC will be able to monitor signals at or below fadc_max @ 3kHz (since the interrupt period is increased by 20 if the ADC is added). At frequencies above these, not only will the PWM and ADC begin to provide inaccurate information, but there will also be increasing switching noise in the circuit.

Since timing is critical for accurate readings, all efforts should be made to make sure that any code executed in the interrupt prior to the ADC code section maintains a uniform execution rate at all times.

The RC network on each analog input/output pin also acts as a low pass filter with a corner frequency of 3.4kHz (R=4.7KW, C=0.01uF). This has been optimized to help reduced the high frequency noise generated by the bitstream switching and the single bit resolution voltage steps. The additional capacitor on each audio output acts a high pass filter and also converts the outgoing signal from DC to AC.

Modifications and further options

With some programming, the SPI and MMC command interpreter subroutines could be changed and the MMC could then be accessed in MMC mode (for SanDisk MMC). This mode would then allow data streaming for read/write operations which would remove the limitations of the block transfers.

More of the MMC functions may be implemented in the command interpreter subroutine and then accessed accordingly. Only the most obvious ones have been implemented here.

The fourth MMC interface pin is to power down the card when it is not in use. If this power saving feature is not required. This pin on the MMC may be tied directly to Vdd freeing up an extra port pin on the SX.

• audio plugin 11a + SX52.brd
• audio plugin 11a + SX52.sch
• MMC 12c.brd
• MMC 12c.sch
• sx52mmc.src MMC plug-in audio demo (SX52) source code

Questions: