Scenix Sxoscope Osc.src

; *****************************************************************************************
; 
; Filename:	Osc.src
;
; Author:	Alberto Geraci
;		BTX Sistemas	
;		Argentina.
;		
; Revision:	1.01
;
; Freq:		50MHz
;
; Compiled using: SX-Key.
;
; Date Written	: Feb 20, 2002
;
; Last Revised	: March 10, 2002
;
; Program Description:
;
;		Super Simple !! SX based oscilloscope:
;		Simple project to demostrate the SX power running at 50Mhz
;		working together with a PC parallel port.
;
; Interface Pins:
;		
;		CLK      equ     rb.6		;A/D clock input
;		D0       equ     rb.7		;A/D data out
;		CS	 equ	 rb.5		;A/D chip select
;		RA.0 and RA.1			;Inputs for selector (time base).				
;		RC port				;Data to be send to PC. (D0 to D7 line).
;		RB.0				;To pin 11 of DB25 (Wait line).		
;		RB.1				;To pin 14 of DB25 (Data Strobe line).
;		
;*****************************************************************************************
;
		device sx28l,stackx_optionx
		device oscxt5,turbo
		freq 50000000
		reset reset_entry

		org 10h
counter 	ds 	 1
data		ds	 1

CLK	equ	rb.6
D0	equ	rb.7
CS	equ	rb.5
;****************************************************************************************************************
;****************************************************************************************************************
		org	20h
reset_entry 	
	 	mov	 ra,#%11111111 			;init rc
		mov 	 !ra,#%00000000
	 	mov	 rc,#%00000000 			;init rc
		mov 	 !rc,#%00000000
	 	mov	 rb,#%00100000 			;init rb
		mov 	 !rb,#%10000010
		mov	w,#$0E		;
		mov	M,w		;
 		mov	!rb,#%011111111	;
		mov	w,#$0F		;
		mov	M,w		;
;
		clr fsr 				;reset all ram banks
:loop 		
		setb 	 fsr.4
		clr 	 ind				; zero all RAM
		ijnz	 fsr,:loop
;
;****************************************************************************************************************
; MAIN
;****************************************************************************************************************
;
main_loop
		; port ra used to change time base X1 // X10 // X100.
		sb	ra.0		; ra.0=0 => one 
		jmp	go_one
		sb	ra.1		; ra.1=0 => ten
		jmp	go_ten
		jmp	go_hundred	; ra.0=1 and ra.1=1 => hundred
;
go_one		call	one		; 128 samples quickly. (max time between samples is the time of convertion).
		jmp	continue
go_ten		call	ten		; 128 samples but 10 times each. ( loosing time ).
		jmp	continue
go_hundred	call	hundred		; 128 samples but 100 times each. ( loosing time ).
		jmp	continue
;							; completed all 128 bytes		
;
		; it is time to send the samples to paralel port.
continue	clr fsr 				;reset all ram banks again
dloop
		setb 	 fsr.4				; same as before
		mov	rc,ind				; data to be send to PC port in RC
out_port						; send each byte of data to parallel port
		clrb	rb.0
npas		snb	rb.1
		jmp	npas
		nop
		setb	rb.0
ready		sb	rb.1
		jmp	ready
;
		ijnz	 fsr,dloop			;  
		jmp	main_loop			; 128 samples sended to paralel port. and all begins ahgain
;******************************************************************************************************************
;		org	400
;****************************************************************************************************************
;   SUB's
;****************************************************************************************************************
get_data				; Step to step get the data out from the ADC
		snb	D0              ; is D0 high or low
		jmp	chi
clo		clrb	$03.0
		rl	data            ;
		ret
chi		setb	$03.0
		rl	data            ;
		ret
;****************************************************************************************************************
conver					; this part of the code, do all the A/D convertion.
		clrb	CLK
		clrb	CS
		nop			; Several nop's to decrease the clk for the ADC08831.
		nop
		nop
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		nop
		nop
		nop
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		call	get_data
;
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		call	get_data
;
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		call	get_data
;
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		call	get_data
;
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		call	get_data
;
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		call	get_data
;
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		call	get_data
;
		setb	CLK
		nop
		nop
		nop
		clrb	CLK
		call	get_data
		setb	CS
		ret
;****************************************************************************************************************
one
		clr fsr 				;reset all ram banks
loopi 		
		setb 	 fsr.4				; inc memory
		mov	counter,#1			; used to simulate time base / 1
anoth
		call	 conver
		decsz 	counter ; 
		jmp	anoth	
;
		mov	 ind,data			; move one byte of data into RAM
		ijnz	 fsr,loopi			; inc bank
		ret
;****************************************************************************************************************
ten
		clr fsr 				;reset all ram banks
tloopi 		
		setb 	 fsr.4				; inc memory
		mov	counter,#10			; used to simulate time base / 10
tanoth
		call	 conver
		decsz 	counter ; 
		jmp	tanoth	
;
		mov	 ind,data			; move one byte of data into RAM
		ijnz	 fsr,tloopi			; inc bank
		ret
;****************************************************************************************************************
hundred
		clr fsr 				;reset all ram banks
hloopi 		
		setb 	 fsr.4				; inc memory
		mov	counter,#100			; used to simulate time base / 100
hanoth
		call	 conver
		decsz 	counter ; 
		jmp	hanoth	
;
		mov	 ind,data			; move one byte of data into RAM
		ijnz	 fsr,hloopi			; inc bank
		ret
;****************************************************************************************************************
END