Our last design example is a surprise. We have only discussed the Z80 CPU thus far in this paper, but there exist some descendants of the Z80. One of these is the Z180. Originally developed by HITACHI, as the 64B180, Zilog now sells this processor as the Z180. HITACHI had some problems with early versions of this chip when connected to Z80 peripheral chips. The Zilog parts have this fixed, as do current production HITACHI parts.
Another Z80 successor chip is the Z280, which is depicted in this design. This processor has a number of peripheral devices built into it. It has three counter/timer channels, four DMA channels, and a UART. This design uses one of the counter inputs to clock the UART.
NOTE : This design example has been successfully implemented. Some of the features of this design do not exist in our previous examples. For example, this design has 32K of static memory, and a Z80 PIO chip. I elected not to remove them so as to preserve the fact that this is a running design.
The actual baud rate clock is generated external to the Z280 as the counter has some funny characteristics, when counting an external signal, that make it undesirable for use as a baud rate generator. If the processor clock were to be selected to be a nice multiple of a baud rate frequency, the counter can divide the CPU clock and generate baud clocks.
The Z280 is a multiplexed address/data bus processor. Further, it can be implemented with either an 8 bit, or 16 bit, data bus. It this example I have chosen to implement the 8 bit data bus. In this mode the Z280 is most like its' cousin, the Z80. A single 74LS373, at U5, is used to de-mux the lower 8 bits of the address from the data bus.
The circuit at the top of page 1 is required to get the CPU started up. There are several bits in the BTI, or Bus Timing and Initialization, register that can only be set in this way. The hardware reset signal from the RC network is connected to a 74LS14, which is a SCHMIDT TRIGGER inverter. This gate will clean up the slow rise time from the RC network and give us a TTL transition. It is inverted again by another section of the 74LS14 to restore the negative true logic. This signal goes to the data inputs of a 74LS164, a shift register. The shift register is constantly clocked by the output clock of the Z280. Five clocks after the data input of the shift register went low, RESET* and STARTUP* will both be low.
The input pulse from the 74LS14 will be on the order of 47ms; a 4.7k pullup and a 100uf cap. When this times out the data input of the shift register will go high. This begins the startup sequence of the Z280. Two clocks later RESET* goes high. Note that the signal STARTUP* is connected to the WAIT* pin of the Z280. When the Z280 comes out of RESET it samples WAIT. If it is low, the data is sampled from the data bus and loaded into the BTI register. The shift register holds STARTUP* low for two clocks after RESET* goes high, then STARTUP* goes high. This circuit then sits idle until the next power up, or manual reset.
On page 2 of the schematics we see the EPROM, static ram, Z80 PIO, and the serial I/O drivers and receivers. The Z280 has a serial port built into it so an SIO chip wasn't necessary for this design.
On page 3 of the schematics we see the DRAM controller. It looks just about like our last design except that the STARTUP flip-flop is gone. It is not needed. The Z280 has enough address space for everything. The PAL directly generates chip selects for everything. Note that the SIMM socket is wired for a 4MB SIMM. This is the biggest SIMM that will fit into a 30 pin module, and it fits nicely into the Z280's address space.
/* Also: CKT5.PDS and compiled JEDEC: CKT5.JED */
;PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE SAMPLE Z280 DESIGN - SYSTEM TIMING GENERATOR
PATTERN PROTO
REVISION A
AUTHOR TIM OLMSTEAD
COMPANY
DATE 08/29/96
CHIP PROTO PAL16L8
;---------------------------------- PIN Declarations ---------------
PIN 1 MREQ ; INPUT
PIN 2 CASIN ; INPUT
PIN 3 A23 ; INPUT
PIN 4 A22 ; INPUT
PIN 5 RD ; INPUT
PIN 6 IORQ ; INPUT
PIN 7 M1 ; INPUT
PIN 8 RFSH ; INPUT
PIN 9 WR ; INPUT
PIN 10 GND ; INPUT
PIN 11 A07 ; INPUT
PIN 12 PIN12 COMBINATORIAL ; OUTPUT
PIN 13 PIN13 COMBINATORIAL ; OUTPUT
PIN 14 PIO COMBINATORIAL ; OUTPUT
PIN 15 RAS COMBINATORIAL ; OUTPUT
PIN 16 CAS COMBINATORIAL ; OUTPUT
PIN 17 SRAM COMBINATORIAL ; OUTPUT
PIN 18 ROM COMBINATORIAL ; OUTPUT
PIN 19 RAMSEL COMBINATORIAL ; OUTPUT
PIN 20 VCC ; INPUT
;----------------------------------- Boolean Equation Segment ------
EQUATIONS
/RAMSEL = /MREQ * A23 * RFSH ; DECODE UPPER 8MB FOR DRAM
+ /MREQ * /RFSH ; REFRESH
/ROM = /A23 * /A22 * /MREQ * /RD ; READ IN FIRST 4MB BLOCK IS ROM
/SRAM = /A23 * A22 * /MREQ ; ANY ACCESS IN SECOND 4MB IS SRAM
/RAS = /MREQ * A23 * RFSH ; DECODE UPPER 8MB FOR DRAM
+ /MREQ * /RFSH * /CASIN ; REFRESH
/CAS = RFSH * /CASIN * /RD ; NORMAL CAS FOR MEMORY READ
+ RFSH * /CASIN * /WR ; HOLD OFF CAS FOR EARLY WRITES
+ /RFSH * /MREQ ; CAS GOES LOW EARLY FOR REFRESH
/PIO = /IORQ * M1 * A07 ; ALL I/O GOES TO PIO FOR NOW
;----------------------------------- Simulation Segment ------------
SIMULATION)0 33 0 0 0 0 250 0 225 2582 sb
;-------------------------------------------------------------------