Data Sheet  App Note

1. Ground all the NC pins (all inputs must be -0.6V to 6.25V with respect to ground; including the NC pins) And just why do they sell a chip that uses only 9 pins in a 28 or 32 pin package?
2. Wait 20ms (1M cycles at 50Mhz) after Vcc reaches 5V before attempting to use the chip. 0.000,000,020
3. /WP to ground (<0.8V) only protects the first 256 pages. Drive it high (>2.0V) (rather than depending on the internal pull-up) if at all possible.
4. /RESET should be driven high (>2.0V) (rather than depending on the internal pull-up) if at all possible. It must be low for at least 10uS (500 cycles at 50Mhz) to have effect.
5. READY/BUSY is the equivalent of the first bit of the status byte. READY/STATUS will be valid (will indicate busy if busy, ready if ready) with in 200nS (10 cycles at 50MHz) of /CS being pulled high (>2.0V).
6. /CS: Driven by host, read by AT45D081, negative logic. Must be high (>2.0V)  for at least 250nS (12.5 cycles at 50MHz) before it is again driven low (<0.08V) between operations and must not be driven low for 20mS (1M cycles at 50Mhz) after Vcc reaches 5V or 1uS (50 cycles at 50MHz) after /RESET is released. Must not be raised untill 250ns (12.5 cycles at 50Mhz) after SCK is placed at the inactive level. After an operation, /CS must remain low for at least 250ns (12.5 cycles at 50MHz) after SCK returns to the inactive level.
7. SCK: SPI mode 0 (Inactive Clock Polarity Low) or 3 (Inactive Clock Polarity High) will be automatically selected on the falling edge (<0.8V) of /CS by sampling the initial polarity of SCK. SCK low = Mode 0, SCK high = Mode 3.
   • SCK must not exceed 10MHz. It also must be high (>2.0V) for at least 40ns then low (<0.08V) for at least 40ns. Since 40ns+40ns is 80ns or 12.5Mhz, an additional 2.5MHz or total of 20ns must be added to the low and or high times. The mid point would be 50ns low or high for 100ns per bit. This is 2 cycles high and 3 low at 50Mhz.
   • This results in a data transfer rate of 1.25MBytes/Sec.
   • SCK must not leave the inactive level for at least 250ns (12.5 cycles at 50MHz) after /CS is driven low and must be at the inactive level for at least 250nS (12.5 cycles at 50MHz) before /CS is raised.
   • The rising edge of SCK always clocks data in and the falling edge clocks data out.
8. SI: Driven by host, read by the AT45D081. Must be stable (high >2.0V or low <0.8V) 10nS (half cycle at 50Mhz) prior to the rising edge of SCK. It must remain stable for at least 25nS (one and a quarter cycles at 50Mhz). Can be tied to the SO Pin Must manage Bus contention
9. SO: Read by host, driven by the AT45D081 when selected. Will be driven (not high impedence) immediately and will be valid (high >2.0V or low <0.8V) 80nS (4 cycles at 50MHz) after the falling edge of SCK if an output is indicated by the operation being performed. It will remain valid through the next SCK cycle and be invalidated immediately by the next falling edge of SCK but will remain driven until 75nS (4 cycles at 50MHz) after the rising edge of /CS. Can be tied to the SI Pin.Must manage Bus contention
10. Power consumption will be less than 20uA in standby (/CS, /RESET, /WP high and all inputs at CMOS levels), less than 25mA during reads and 50mA during writes.
11. Including the overhead for specifying an address and /CS delays results in the following (optimal) timings:

    Operation	Read			Write
    	per Sec	Seconds	cycles at 50Mhz	per Sec	Seconds	cycles at 50Mhz
    Issue a command			186 (13+4*8*5+13)
    Address buffer and transfer one byte	164k	6.10uS	306 (13+7*8*5+13)	188k	5.30uS	226(13+5*8*5+13)
    Address buffer and transfer 16bytes	55.4k	18.1uS	906 (13+22*8*5+13)	57.8k	17.3uS
    Address buffer and transfer one 256B page	4.76k	210uS	10506 (13+262*8*5+13)	4.78k	209uS
    Address FLASH and transfer one byte	130k	7.70uS	346 (13+8*8*5+13)	50-100	7-20mS	350,226 - 1,000,226 (13+5*8*5+13+1M)
    Address / xfer page to / from FLASH	6.5k-12k	83-153uS	4186-7686 (13+4*8*5+13+7500)	50-100	7-20mS	350,226 - 1,000,186 (13+4*8*5+13+1M)

    
    Obviously, write caching is a big winner on the chip (i.e. write all the bytes in one page to the buffer then FLASH the buffer) and on the host (keep multiple pages in RAM and only write when the memory is not busy). Read caching is good if 10% of your reads hit within the same page (very likely even when doing non-sequential reads). It takes 10 times as long to get an entire page into a buffer as it does to read a single byte but then it takes about the same time to read the bytes and you read other bytes on that page while loading or storing the other buffer.
    
    Some time could be saved by formating unused sectors in advance thus reduceing the page write delay to 7-14ms, or 350,000-700,000 cycles at 50Mhz.
    
    Time to read a page of FLASH compared to the time to write a page of flash is about 130 to 1 (80:e-6 to 150:e-6 Seconds vs 10:e-3 to 20:e-3 Seconds) and the time to read a buffer compared to the time to load a buffer from flash is about 50 to 1. (210:e-6 vs 10:e-3)
    

12. Minimum granularity for all operations appears to be 50nS or 20MHz (I.e. we only have to look at the chip once every 50nS for anything). That is 2.5(3) cycles on a 50MHz processor or 5 cycles on a 100MHz processor (much too fast to handle in an ISR. The next time interval is 250nS (/CS delay, or xfer 2 bits) at 12.5 cycles (still to fast for an ISR). Then about 10uS(to read or write one byte or issue a command) at 500 cycles (306 cycles in ISR which is kind of big for an ISR). 20uS(to read or write 16 bytes / read or write 8 bytes and issue a command) at 1000 cycles (906/812 in ISR which is too big.).
13. Need to track variables
    • Am I starting a new operation? (so that the code can get /CS low right away and then do other stuff for 12 or 13 cycles)
    • Bit value being sent or received
    • Which bit of a byte we are sending or receiving.
    • Current address (2 bytes for page, 1 byte for byte in page, 1 bit for extra bytes in page)
14. Subroutine library should include:
    • Start Operation
      • Is an operation in process?
        • Call End Operation
      • Has it not been 1Mcycles since power up, 50 cycles since reset and 13 cycles since release of /CS?
        • Wait
      • Release SCK
      • Assert /CS (low)
      • Wait 250 uSec
    • Send a bit (macro) setup by Shifting data byte one bit right, and getting the carry
      • Copy carry bit to SI
      • Shift data byte one bit right
      • Wait 1 cycle (already done by previous step) then Raise SCK
      • Get the carry from the shift
      • Wait 2 cycles (1 already done by previous step) then Drop SCK
    • Send a byte (send 8 bits)
    • Get a bit (macro)
      • Copy SI to carry bit
      • Wait 1 cycle (already done by previous step) then Raise SCK
      • Shift carry bit into data byte
      • Drop SCK then Wait 2 cycles (1 already done by previous step)
    • Get a byte (get 8 bits)
    • Send each of the possible opcodes
    • Send page/byte/buffer address
    • Complete an Operation
    • Set starting address
    • • Is the new address not the same as the current address?
        • Is the new address not in the same page?
          • Are there no free buffers?
            • Flush the least frequently used buffer: Op 88h or 89h
          • start reading the page from FLASH
    • Read Byte
      • Is the byte not in the local cache (this may be a single byte)?
        • Is the page not in one of the two buffers?
          • are there no free buffers (all buffers contain data to be written)?
            • Flush the least frequently used buffer: Op 88h or 89h
          • start reading the page from FLASH to the available buffer: Op 53h or 55h
        • Is the buffer not ready (being read or written to FLASH)?
          • Wait for the buffer to become ready.
        • Start reading the buffer to the local cache.
      • Increment the local cache, buffer and FLASH address pointers
      • Return the bytes from the local buffer.
    • Store Byte
    • Flush Buffers

Op Codes

A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first.

Device Status

CS{to low}, out: 57H. in: (status: 1 bit)(result: 1 bit)(density: 3 bits)(unused: 3 bits), CS(to high)

The status register can be used to determine the device’s ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H must be loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five most-significant bits of the status register will contain device information, while the remaining three least-significant bits are reserved for future use and will have undefined values.

After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so each repeating sequence will output new data.

After

1. Main Memory Page to Buffer Transfer
2. Main Memory Page to Buffer Compare,
3. Buffer to Main Memory Page Program with Built-In Erase,
4. Buffer to Main Memory Page Program without Built-In Erase
5. Main Memory Page Program
6. Auto Page Rewrite.

Check the device status by sending opcode 57H and then clocking bit 7 (the MSB) of the status register back out on the SO pin. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state.

The user can continuously poll bit 7 of the status register by stopping SCK once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and once the device is no longer busy, the state of SO will change from 0 to 1.

The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer.

The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45D081, the three bits are 1, 0, and 0. The decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial Data flash devices, allowing a total of eight different density configurations.

Read

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers.

MAIN MEMORY PAGE READ:

A main memory read allows the user to read data directly from any one of the 4096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don’t care bits. In the AT45D081, the first three address bits are reserved for larger density devices, the next 12 address bits (PA11-PA0) specify the page address, and the next nine address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care bits which follow the 24 address bits are sent to initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, and the reading of data. When the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. A low to high transition on the CS pin will terminate the read operation and tri-state the SO pin.

BUFFER READ:

Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H is used to read data from buffer 1, and an opcode of 56H is used to read data from buffer 2. To perform a buffer read, the eight bits of the opcode must be followed by 15 don’t care bits, nine address bits, and eight don't care bits. Since the buffer size is 264-bytes, (8 bytes more than the standard 256) nine address bits (BFA8-BFA0) are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low to high transition on the CS pin will terminate the read operation and tri-state the SO pin.

MAIN MEMORY PAGE TO BUFFER TRANSFER:

A page of data can be transferred from the main memory to either buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and 55H for buffer 2, is followed by the three reserved bits, 12 address bits (PA11-PA0) which specify the page in main memory that is to be transferred, and nine don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (t XFR ), the status register can be read to determine whether the transfer has been completed or not.

Note: While the state machine is busy transferring data from one buffer to the main memory page, the other buffer may be read from or written to. This feature of the Serial Data flash allows a virtually continuous write operation provided each of the buffers is not filled faster than the maximum page erase and program time (data cannot be clocked in at a rate in which the time to fill a buffer is less than the maximum t EP time specified in the data sheet).

CAUTION

To preserve data integrity, each page in the Data flash memory array must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. See Auto Page Re-Write and Application Note AN-4 (“Using Atmel’s Serial Data flash”) for more details.

MAIN MEMORY PAGE TO BUFFER COMPARE:

A page of data in main memory can be compared to the data in buffer 1 or buffer 2. An 8-bit opcode, 60H for buffer 1 and 61H for buffer 2, is followed by 24 address bits consisting of the three reserved bits, 12 address bits (PA11-PA0) which specify the page in the main memory that is to be compared to the buffer, and nine don't care bits. The loading of the opcode and the address bits is the same as described previously. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don't care bits from the SI pin. On the low to high transition of the CS pin, the 264 bytes in the selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2. During this time (t XFR ), the status register will indicate that the part is busy. On completion of the compare operation, bit 6 of the status register is updated with the result of the compare. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer.

Note: While the state machine is busy transferring data from one buffer to the main memory page, the other buffer may be read from or written to. This feature of the Serial Data flash allows a virtually continuous write operation provided each of the buffers is not filled faster than the maximum page erase and program time (data cannot be clocked in at a rate in which the time to fill a buffer is less than the maximum t EP time specified in the data sheet).

Program

BUFFER WRITE:

Data can be shifted in from the SI pin into either buffer 1 or buffer 2. To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, is followed by 15 don't care bits and nine address bits (BFA8-BFA0). The nine address bits specify the first byte in the buffer to be written. The data is entered following the address bits. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low to high transition is detected on the CS pin.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE:

Data written into either buffer 1 or buffer 2 can be programmed into the main memory. An 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, is followed by the three reserved bits, 12 address bits (PA11-PA0) that specify the page in the main memory to be written, and nine additional don't care bits. When a low to high transition occurs on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page are internally self timed and should take place in a maximum time of t EP . During this time, the status register will indicate that the part is busy.

Note: While the state machine is busy transferring data from one buffer to the main memory page, the other buffer may be read from or written to. This feature of the Serial Data flash allows a virtually continuous write operation provided each of the buffers is not filled faster than the maximum page erase and program time (data cannot be clocked in at a rate in which the time to fill a buffer is less than the maximum t EP time specified in the data sheet).

CAUTION

To preserve data integrity, each page in the Data flash memory array must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. See Auto Page Re-Write and Application Note AN-4 (“Using Atmel’s Serial Data flash”) for more details.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-OUT BUILT-IN ERASE:

A previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1 or 89H for buffer 2, is followed by the three reserved bits, 12 address bits (PA11-PA0) that specify the page in the main memory to be written, and nine additional don’t care bits. When a low to high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main memory that is being programmed has been previously programmed to all 1s (erased state). The programming of the page is internally self timed and should take place in a maximum time of t P . During this time, the status register will indicate that the part is busy.

Note: While the state machine is busy transferring data from one buffer to the main memory page, the other buffer may be read from or written to. This feature of the Serial Data flash allows a virtually continuous write operation provided each of the buffers is not filled faster than the maximum page erase and program time (data cannot be clocked in at a rate in which the time to fill a buffer is less than the maximum t EP time specified in the data sheet).

CAUTION

To preserve data integrity, each page in the Data flash memory array must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. See Auto Page Re-Write and Application Note AN-4 (“Using Atmel’s Serial Data flash”) for more details.

MAIN MEMORY PAGE PROGRAM:

This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-In Erase operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in the main memory. An 8-bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed by the three reserved bits and 21 address bits. The 12 most significant address bits (PA11-PA0) select the page in the main memory where data is to be written, and the next nine address bits (BFA8-BFA0) select the first byte in the buffer to be written. After all address bits are shifted in, the part will take data from the SI pin and store it in one of the data buffers. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low to high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page are internally self timed and should take place in a maximum of time t EP . During this time, the status register will indicate that the part is busy.

Note: While the state machine is busy transferring data from one buffer to the main memory page, the other buffer may be read from or written to. This feature of the Serial Data flash allows a virtually continuous write operation provided each of the buffers is not filled faster than the maximum page erase and program time (data cannot be clocked in at a rate in which the time to fill a buffer is less than the maximum t EP time specified in the data sheet).

CAUTION

To preserve data integrity, each page in the Data flash memory array must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. See Auto Page Re-Write and Application Note AN-4 (“Using Atmel’s Serial Data flash”) for more details.

AUTO PAGE REWRITE:

This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion. To preserve data integrity, each page in the Data flash memory array must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. The user could count through and re-write pages sequentially, (one after each change to any main memory page) so that after 4096 main memory page writes, the entire memory has been refreshed. {ed: can't we do one every other change so that after 8192 writes the entire memory is refreshed?}. Another method is to track the number of writes in-order to delay the re-write operation until 10,000 erase/program operations have accumulated and then re-write the entire memory. See application note AN-4 (“Using Atmel’s Serial Data flash”) for more details.

This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-In Erase. A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. An 8-bit opcode, 58H for buffer 1 or 59H for buffer 2, is followed by the three reserved bits, 12 address bits (PA11-PA0) that specify the page in main memory to be rewritten, and nine additional don't care bits. When a low to high transition occurs on the CS pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. The operation is internally self-timed and should take place in a maximum time of t EP . During this time, the status register will indicate that the part is busy.

Note: While the state machine is busy transferring data from one buffer to the main memory page, the other buffer may be read from or written to. This feature of the Serial Data flash allows a virtually continuous write operation provided each of the buffers is not filled faster than the maximum page erase and program time (data cannot be clocked in at a rate in which the time to fill a buffer is less than the maximum t EP time specified in the data sheet).

See also:

• http://x23.deja.com/[ST_cam=search.yahoo.none.slot]/getdoc.xp?AN=520311038.1&CONTEXT=938097151.459472917&hitnum=19
• SPI to Atmel Dataflash PIC C Routine